IAN LANG ELECTRONICS

Digital Logic

 Which in words means to say that the gate only gives a high output if both its inputs are low. If we look at our required output Q, we find the expression in brackets is an Or one, as we are adding together , and the whole is an And, as we are multiplying.
This makes things tricky.

However if we apply De Morgan's Law we can make the whole thing an expression of Or statements and construct our Nand circuit around that.
De Morgan's Law consists of two theorems that state:

And once again because of practical problems in electronic typefacing it is common to write (A+B)'= (AB)' and (AB)' = (A+B)'
This is rather esoteric mathematics and the practical outcome in words in the first theorem is that the complement of the output of ORing A and B is equal to the output of ANDing the complements of A and B. In the second the complement of the output of ANDing A and B is the same as ORing the complements of A and B. A complement means merely the opposite, and in digital logic there are only two conditions, 0 and 1, and so each is the complement of the other.
Applying De Morgan's Law to (A+B)(A+C) gives us (A+B)' + (A+C)' and turns the whole thing into an Or. However if we negate only once we get the inverse of what we need and so we double negate.

Our expression becomes:

The first four Nand gates and the two thereafter comprise our Or gate and because the first four are Nands our first inversion comes about automatically. The last gate in the chain provides our second inversion, providing us with the output required .